1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More particularly, the invention relates to a phase change memory device adapted to compensate for leakage current in a read operation.
A claim of priority is made to Korean Patent Application No. 2005-0012746 filed on Feb. 16, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values, which are used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance, and the crystalline phase exhibits a relatively low resistance.
At least one type of phase change memory device—phase change random access memory (PRAM)—uses the amorphous state to represent a logical ‘1’ and the crystalline state to represent a logical ‘0’. In a PRAM device, the crystalline state is referred to as a “set state”, and the amorphous state is referred to as a “reset state”. Accordingly, a memory cell in a PRAM stores a logical ‘0’ by “setting” a phase change material in the memory cell to the crystalline state, and the memory cell stores a logical ‘1’ by “resetting” the phase change material to the amorphous state. Various PRAM devices are disclosed, for example, U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase change material in a PRAM is converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material. The phase change material is converted to the crystalline state by heating the material at another predetermined temperature below the melting temperature for a set period of time. Accordingly, data is written to memory cells in a PRAM by converting the phase change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described.
The phase change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), i.e., a “GST” compound. The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling.
The memory cells in a PRAM are called “phase change memory cells”. A phase change memory cell typically comprises a top electrode, a chalcogenide layer, a bottom electrode contact, a bottom electrode, and an access transistor. In the phase change memory cell, the chalcogenide layer is the phase change material. Accordingly, a read operation is performed on the phase change memory cell by measuring the resistance of the chalcogenide layer, and a write operation is performed on the phase change memory cell by heating and cooling the chalcogenide layer as described above.
FIGS. 1A and 1B illustrate a conventional phase change memory cell 100 in two different states. In particular, FIG. 1A shows phase change memory cell 100 with a phase change layer (e.g., a chalcogenide layer) in the crystalline state, and FIG. 1B shows phase change memory cell 100 with the phase change layer is in the amorphous state.
Referring to FIGS. 1A and 1B, phase change memory cell 100 comprises a top electrode 12 formed on a phase change layer 14, and a bottom electrode contact (BEC) 16 connecting top electrode 12 to a bottom electrode 18 through phase change layer 14.
In FIG. 1A, memory cell 100 is in the “set state”, and therefore stores a logical ‘0’, and in FIG. 1B, memory cell 100 is in the “reset state”, and therefore stores a logical ‘1’.
Memory cell 100 further comprises an access transistor N20 to control the flow of current through phase change layer 14. When current flows through phase change layer 14, bottom electrode contact 16 acts as a heater to heat phase change layer 14 and change its state. Access transistor N20 typically comprises a negative metal-oxide semiconductor (NMOS) transistor.
FIG. 2 is a circuit diagram of memory cell 100 shown in FIG. 1. In FIG. 2, top electrode 12, phase change layer 14, BEC 16, and bottom electrode 18 are represented as a phase change resistance element “R”.
Referring to FIG. 2, memory cell 100 is controlled by a word line WL and a bit line BL. Wordline WL controls whether access transistor N20 is turned on and bitline BL provides a voltage for a current “ICELL” flowing through access transistor N20. Current “ICELL” flows through memory cell 100 when wordline WL and bitline BL are both activated. Wordline WL and bitline BL are used for both programming and reading memory cell 100.
FIG. 3 is a timing diagram illustrating a programming operation of memory cell 100. In particular, FIG. 3 shows how time and a temperature applied to phase change layer 14 are used to program memory cell 100.
Referring to FIG. 3, a first curve 35 shows a time/temperature combination used to place memory cell 100 in the “reset state”, and a second curve 36 shows a time/temperature combination used to place memory cell 100 in the “set state”.
As shown in curve 35, phase change layer 14 is heated above a melting point “Tm” and then quickly cooled to change it to the amorphous state. As shown in curve 36, phase change layer 14 is heated to an intermediate temperature between melting point “Tm” and a crystalline temperature “Tx” for a predetermined amount of time, and then cooled to change it to the crystalline state. In FIG. 3, melting point “Tm” is set to 610° C. and crystalline temperature “Tx” is set to 450° C. However, these temperatures can be varied within reasonable ranges and still perform their desired function.
FIG. 4 illustrates a relationship between the voltage across phase change layer 14 and the amount of current flowing through phase change layer 14. Typically, the voltage across phase change layer 14 is varied by changing the voltage on bitline BL.
Referring to FIG. 4, phase change layer 14 performs very differently in the set state and the reset state. In FIG. 4, a symbol □ labels a curve showing the amount of current passing through phase change layer 14 in the reset state, and a symbol □ labels a curve showing the amount of current flowing through phase change layer 14 in the set state. A symbol □ labels a curve showing the amount of current flowing through phase change layer 14 when it is being programmed.
As seen in FIG. 4, a program voltage above a predetermined threshold voltage Vth is applied to bitline BL to program memory cell 100, and a read voltage below threshold voltage Vth is applied to bitline BL to read memory cell 100.
FIG. 4 shows an exemplary voltage level “Vread” used to read memory cell 100. When the voltage across phase change layer 14 has voltage level Vread, the current passing through phase change layer 14 has a level “Iread”. A typical value for Vread is 0.4 to 0.6 times Vth.
Unfortunately, whenever a read voltage is applied to memory cell 100, leakage current escapes through non-selected memory cells that share bitline BL. As a result, the resistance of phase change layer 14 may be incorrectly read. Leakage currents become increasingly problematic as the size and power consumption of phase change memory devices becomes smaller, because as they do, their margin of error also decreases.